CMOS Inverter Working Principle

Why the inverter matters

The inverter is the simplest CMOS logic gate, and its behaviour defines how all CMOS logic works. NAND, NOR and complex gates use the same idea: a pull-up network of PMOS transistors and a complementary pull-down network of NMOS transistors. Understanding the inverter’s switching threshold, delay and power explains the speed and power limits of entire chips.

Circuit structure

Download diagram (WebP)

• The PMOS source is connected to the supply VDD. It turns on when its gate is low relative to its source.
• The NMOS source is connected to ground. It turns on when its gate is high.
• Both gates connect to the input; both drains connect to the output, which drives the next gate’s input capacitance.

How the CMOS inverter works

With the input low, the PMOS connects the output to VDD and the NMOS is off, so the output is a strong logic 1. With the input high, the NMOS connects the output to ground and the PMOS is off, so the output is a strong logic 0. The output swings fully from rail to rail, which gives CMOS large noise margins.

Voltage transfer characteristic

Plotting Vout against Vin as the input sweeps from 0 to VDD gives the voltage transfer characteristic (VTC). It has a flat high region, a steep transition and a flat low region. Inside the transition region both transistors conduct briefly.

• The switching threshold VM is the input voltage at which Vin = Vout. For balanced transistors it is close to VDD / 2.
• VIL and VIH are the input voltages where the slope of the VTC is −1. Inputs below VIL are safely read as 0, and above VIH as 1.
• The noise margins are NML = VIL − VOL and NMH = VOH − VIH. Because VOL ≈ 0 and VOH ≈ VDD, CMOS noise margins are large.

Transistor sizing

The current a MOSFET can drive is proportional to its carrier mobility and its width-to-length ratio W/L. Electron mobility in silicon is roughly two to three times hole mobility, so an NMOS of the same size is stronger than a PMOS. To make the rise and fall times equal and place VM near VDD / 2, the PMOS is usually made about two to three times wider than the NMOS. Designers can deliberately skew the sizes to move VM or to speed up one transition.

Propagation delay

The inverter output drives a load capacitance made up of the next gates’ inputs, the wiring and its own drain capacitance. Each transition charges or discharges this capacitance through the resistance of the conducting transistor. The propagation delay is therefore roughly proportional to the product of the effective transistor resistance and the load capacitance. Larger transistors switch heavier loads faster but present more capacitance to the gate that drives them, which is the basis of buffer sizing techniques such as logical effort.

Power consumption

CMOS power has three parts:

• Dynamic switching power, from charging and discharging the load capacitance:

$$P_{dyn} = \alpha\, C_L\, V_{DD}^2\, f$$

where α is the activity factor (the fraction of clock cycles in which the node switches), CL the load capacitance and f the clock frequency.

• Short-circuit power, during the brief time in each transition when both transistors conduct.
• Static (leakage) power, from subthreshold and gate leakage currents. It was negligible in older processes but is significant in modern nanometre processes.

From inverter to NAND and NOR

Other CMOS gates extend the inverter’s complementary structure:

• NAND gate: two NMOS transistors in series in the pull-down network and two PMOS transistors in parallel in the pull-up network. The output goes low only when both inputs are high.
• NOR gate: two NMOS transistors in parallel in the pull-down network and two PMOS transistors in series in the pull-up network. The output goes high only when both inputs are low.

Because PMOS transistors are weaker, series PMOS stacks are slow. NAND gates, which put the series stack in the stronger NMOS network, are therefore usually preferred to NOR gates in CMOS design.

Why CMOS dominates digital design

• Very low static power, which makes high gate density possible.
• Full rail-to-rail output and large noise margins.
• High input impedance, since MOSFET gates draw no DC current.
• Scalability: shrinking transistor dimensions increases speed and density, which has driven decades of progress in processors and memory.

Supply voltage scaling

Because dynamic power depends on VDD squared, supply voltages have fallen with each process generation, from 5 V in early CMOS to around 1 V or less in modern processors. Lower voltage reduces power and allows smaller transistors, but it also reduces the current drive, slows switching and shrinks noise margins, so the threshold voltages of the transistors must be reduced too, which increases leakage.

Applications

The CMOS inverter is used as a buffer and clock driver, as a building block of ring oscillators for process monitoring, and as the basis of SRAM cells, where two cross-coupled inverters store one bit. Every CMOS logic gate in a processor, FPGA or microcontroller is an extension of the same complementary pull-up and pull-down principle.

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